Method of driving liquid crystal panel, and liquid crystal display apparatus

ABSTRACT

A liquid crystal display apparatus drives an active-matrix liquid crystal panel by the use of the line reversal driving method. To do so, a common driver AC-drives one of a pair of electrode in each of all the pixels of the liquid crystal panel. An adding circuit obtains the sum of a plurality of gradation components for deciding the gradations of the pixels in one of the columns in the liquid crystal panel at intervals of the predetermined horizontal period. A voltage setting portion in a source driver corrects a reference voltage difference  66  Vref on the basis of the sum at intervals of the horizontal period, divides the corrected reference voltage difference  66  Vrefa, decides a plurality of gradation voltages, and selects voltages to be applied to a plurality of data lines in the liquid crystal panel from among the gradation voltages based on the plurality of gradation components. The selected plurality of voltages are applied to the plurality of data lines.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of driving a liquid crystalpanel and a liquid crystal display apparatus for displaying high-qualityimages when multicolor display or full-color display is performed orwhen the liquid crystal panel for displaying an image is increased insize.

2. Description of the Related Art

A conventional active-matrix liquid crystal display apparatus using athin-film transistor (hereinafter, referred to as “TFT”) includes aliquid crystal panel comprising a plurality of pixels arranged in amatrix form, and a liquid crystal driving portion for supplying electricsignals to the liquid crystal panel. The pixels each have a structuresuch that liquid crystal is sandwiched between a pixel electrode and acounter electrode. In addition to the plurality of pixels, the liquidcrystal panel includes a plurality of scanning lines, a plurality ofdata lines and a plurality of TFTs. The pixel electrode in each pixel isconnected to one of the data lines through one of TFTs. The counterelectrodes of all the pixels are interconnected to one another to formone common electrode. The liquid crystal driving portion includes a gatedriver for supplying electric signals to the scanning lines, a sourcedriver for supplying electric signals to the data lines, and the commonelectrode.

FIG. 10 is a block diagram showing the electric structure of the sourcedriver 1. The source driver 1 includes an input latch circuit 2, a shiftregister 3, a sampling memory 4, a hold memory 5, a D/A converter 6, agradation-voltage-generating circuit 7 and an output circuit 8. Thesource driver 1 is supplied with the image data representative of theimage to be displayed. The image data comprises data for expressing thebrightness, chroma and hue of each image element forming the image. Eachimage element of the image corresponds to a set of three pixels havingred, blue and green color filters, respectively, in the liquid crystalpanel. Therefore, each image element data comprises three kinds ofgradation components, namely, so-called R (red), G (green) and B (blue)components, and the gradation components represent 64 levels ofgradations.

First, the three kinds of gradation components in each image elementdata are successively supplied to the input latch circuit 2 to belatched. Based on a synchronizing signal SPI supplied from a controlcircuit disposed outside the source driver 1 through the shift register3 that operates in response to a clock signal CK, the sampling memory 4samples the image data latched by the input latch circuit 2.Consequently, a part of the image data which part is associated with anelectric signal to be supplied from the source driver 1 to the liquidcrystal panel within a single horizontal period 1H, that is, a pluralityof gradation components that decide the gradations of a plurality ofpixels constituting one of the rows in the liquid crystal panel arestored in the sampling memory 4. The plurality of gradation componentsare transferred from the sampling memory 4 to the hold memory 5 insynchronism with a synchronizing signal LS of the horizontal period ofthe liquid crystal panel.

The hold memory 5 latches the plurality of gradation components beingtransferred, and supplies the plurality of gradation components to theD/A converter 6. The gradation-voltage-generating circuit 7 divides thedifference between predetermined two reference voltages Vref1 and Vref2,decides 64 kinds of gradation voltages and supplies the gradationvoltages to the D/A converter. The gradation voltages each correspond toone of the 64 levels of gradations that the pixels can take. The D/Aconverter 6 selects from among the 64 kinds of gradation voltages thegradation voltages that correspond to the gradations shown by theplurality of gradation components being supplied, and supplies theselected gradation voltages to the output circuit 8. The output circuit8 impedance-converts the selected gradation voltages and charges ordischarges the source lines of the liquid crystal panel in accordancewith the impedance-converted gradation voltages. Consequently, to thesource lines of the liquid crystal panel, electric signals of voltagesbased on the image data are supplied as so-called data signals.

In each of the pixels, since the pixel electrode and the counterelectrode act as electrodes of a capacitor, a capacitance called, forexample, parasitic capacitance is present. That is, data signals inaccordance with the voltages to be held by the pixels are supplied fromthe source driver to the data lines and the states of the TFTs arechanged, whereby the voltages can be written into the pixels so as to beheld by the pixels.

For example, with respect to one of all the TFTs, when the voltage of anelectric signal, namely, a so-called scanning signal, supplied from thegate driver to the scanning line to which the gate terminal of the TFTis connected becomes positive, a positive voltage is applied to the gateterminal, so that the one of the TFTs changes to a so-called ON state.Consequently, the pixel including the pixel electrode to which the oneof the TFTs is connected is charged by the voltage applied to the dataline to which the one of the TFTs is connected. When the voltage of thescanning signal becomes negative, a negative voltage is applied to thegate terminal, so that the one of the TFTs changes to so-called OFFstate. Consequently, the voltage between the pixel electrode and thecounter electrode in the pixel is maintained at the voltage appliedbetween the pixel electrode and the counter electrode when the one ofthe TFTs changes to OFF state. As a result, the voltage to be held iswritten into the pixel. The transmittance of the liquid crystal layer inthe pixel, that is, the gradation of the pixel is decided in accordancewith the voltage held by the pixel. Therefore, by controlling thegradations of all the pixels in the liquid crystal panel by the voltagesheld by the pixels, an image is displayed on the liquid crystal panel.

The liquid crystal panel is reversely driven in order that the liquidcrystal is not polarized. Reverse driving methods include a so-calleddot reversal driving method and a so-called line reversal drivingmethod. In the description that follows, it is assumed that the pixelsof the liquid crystal panel are arranged in 6 rows and 5 columns.

First, the behavior of the liquid crystal display apparatus of theabove-described structure when the liquid crystal display apparatus isdriven by the line reversal driving method will be described. FIG. 11shows a timing chart of a plurality of scanning signals 11 a to 11 fsupplied from the gate driver in the liquid crystal display apparatus tosix scanning lines. FIG. 12 shows a timing chart of one scanning signal11 of the scanning signals 11 a to 11 f, one data signal 12 of aplurality of data signals supplied from the source driver 1 to five datalines, and a voltage 13 applied to the common electrode in the liquidcrystal display apparatus. FIGS. 11 and 12 will be described together.

The scanning signals 11 a to 11 f are held at high level during apredetermined single horizontal period WH at intervals of apredetermined frame display period CH, and are held at low level duringthe remaining period. The timing where the plurality of scanning signals11 a to 11 f are held at high level within a time period correspondingto one cycle of a horizontal synchronization cycle differs among thesignals. Therefore, to all the pixels in the row of pixels on one of thescanning lines, the voltage to be held is written while the scanningsignal supplied to the one of the scanning lines is held at a highlevel. The row as pixels on one of the scanning lines is a set of aplurality of pixels including pixel electrodes connected to the drainterminals of a plurality of TFTs whose gate terminals are connected tothe one of the scanning lines.

The cycle of the alternating component of the voltage 13 applied to thecommon electrode equals the horizontal period WH. That is, when the linereversal driving method is used, the common electrode is AC-driven in acycle the same as the horizontal period WH by a single 5-V power source.The alternating component of the data signal 12 changes in apredetermined cycle that is shorter than the horizontal period WH aroundthe center of amplitude of the alternating component of the voltage 13applied to the common electrode. The amplitude of the alternatingcomponent of the data signal 12 varies according to the gradation of thepixel. The alternating component of a data signal 12 a of a case wherethe gradation of the pixel is maximum, that is, a case where the pixelrepresents black is opposite in polarity to the alternating component ofa data signal 12 b of a case where the gradation of the pixel isminimum, that is, a case where the pixel represents white. Theamplitudes of the data signals 12 a and 12 b of the cases where thegradation of the pixel is maximum and where the gradation is minimum areboth smaller than the amplitude of the alternating component of thevoltage 13 applied to the common electrode.

The arrow 14 indicates the polarity of the current flowing through thepixel in order to write the voltage to be held into the pixel, that is,whether or not the voltage held by the data line is higher than thevoltage held by the common electrode when the voltage to be held iswritten into the pixel. When the arrow 14 points upward, since thevoltage of the data line is higher than the voltage of the commonelectrode, the polarity is positive. When the arrow 14 points downward,since the voltage of the data line is lower than the voltage of thecommon electrode, the polarity is negative. When the polarity ispositive, the current flows from the data line through the pixel to thecommon electrode. When the polarity is negative, the current flows fromthe common electrode through the pixel to the data line.

FIG. 13A shows the polarities of the currents in all the pixels. Thecurrents are for writing the voltages to be held into all the pixels inthe liquid crystal panel in a given frame in case where the liquidcrystal display apparatus is driven by the use of the line reversaldriving method. FIG. 13B shows the polarities of the currents in all thepixels in a frame next to the frame of FIG. 13A in the above-mentionedcase. The plural rectangles arranged in a matrix correspond to thepixels in the liquid crystal panel of 6 rows and 5 columns. The rows ofthe rectangles correspond to the rows of pixels. The columns of therectangles correspond to the columns of pixels, that is, sets of all thepixels including the pixel electrodes connected to one given data linethrough the TFTs. When the polarity of the current flowing through apixel is positive, “+” is drawn in the rectangle corresponding to thepixel. When the polarity is negative, “−” is drawn in the rectangle.

The polarity of the current flowing through one given pixel of theliquid crystal panel is reversed between the first frame and the nextframe. In both of the first and the next frames, the polarities of thecurrents flowing through two adjoining pixels in one column aredifferent from each other and the polarities of the currents flowingthrough all the pixels in one row are equal to one another.Consequently, the currents concentrate at the common electrode, so thata voltage drop is apt to occur at the common electrode. When a voltagedrop occurs, it is impossible to correctly write the voltages to be heldinto the pixels, so that the display quality of the liquid crystaldisplay apparatus is reduced.

A cause of display quality reduction of the liquid crystal displayapparatus when the liquid crystal display apparatus is driven by the useof the line reversal driving method will be described in detail by theuse of an equivalent circuit of the liquid crystal display apparatus ofFIG. 14. In FIG. 14, it is assumed that the pixels of a liquid crystalpanel 20 are arranged in 2 rows and 2 columns, and the common electrodeis shown as a plurality of counter electrodes 22 successively connectedby conductors 25 each having an internal resistance component rc.

For example, it is assumed that the voltages to be held are written intopixels 21 a and 21 b on the first scanning line 24 a from the top by apositive-polarity current. In this case, the voltage of the scanningsignal supplied to the first scanning line 24 a based on an output 23 afrom the gate driver is a voltage capable of turning on the TFTs,whereas the voltage of the scanning signal supplied to the secondscanning line from the top based on an output 23 b from the gate driveris a voltage capable of turning off the TFTs. In the above-describedcase, the currents flowing into the pixels 21 a and 21 b of the row onthe first scanning line 24 a flow, as shown by the broken line 30, fromdata lines 26 a and 26 b through TFTs 27 a and 27 b and pixels 28 a and28 b to parts 29 on the side of the common electrode.

As described above, when the polarities of the currents written into allthe pixels of the row on one given scanning line are equal to oneanother, the directions of the currents flowing through all the pixelsare equal to one another. Therefore, the currents flowing out of all thepixels concentrate at the common electrode, so that a voltage dropoccurs due to the resistance components rc of the conductors 25interposed between the counter electrodes 22 and the internal resistanceRc of the parts 29 on the side of the common electrode.

Consequently, as shown in FIG. 15, the actual voltage Vα between thecommon electrode and the pixel electrode is lower than the difference Vβbetween the voltage of the data signal and the voltage applied to thecommon electrode by the amount Vγ of the voltage drop. That is, thevoltage actually held by the common electrode is closer to the voltageof the common electrode than a voltage to be intrinsically held by thepixel electrode by the voltage drop amount Vγ.

The voltage drop amount Vγ varies according to the voltage of the datasignal. For example, the voltage drop amount Vγ is largest when all ofthe voltages of all the data signals supplied to the liquid crystalpanel within the horizontal period WH are the highest pixel voltage ofthe pixel voltages of the 64 gradations. Moreover, for example, thevoltage drop amount is smallest when all of the voltages of all the datasignals are the lowest pixel voltage of the pixel voltages of the 64gradations. The levels of all the data signals are decided in accordancewith the gradation distribution of the image elements of one of the rowsin the image represented by the image data and the gradationdistributions of the image elements of the rows in the image frequentlydiffer from one another. Therefore, the levels of all the data signalschange at intervals of a horizontal period, that is, every time the rowinto which the voltage to be held is written is changed.

Consequently, when a sheet of image is displayed on the liquid crystalpanel, so-called gradation nonuniformity is caused in the image. Furtherwhen an image in which there is a black window against a halftonebackground is displayed on the liquid crystal display apparatus, theperipheral part of the black window in the background is whiter than thepart other than the peripheral part in the background. Therefore, in theabove-described case, so-called lateral shadowing becomes a problem.From the above, when the liquid crystal display apparatus is driven bythe use of the line reversal driving method, the display quality of theliquid crystal display apparatus is reduced.

Hereinafter, the behavior of the liquid crystal display apparatus of theabove-described structure when the liquid crystal apparatus is driven bythe dot reversal driving method will be described. FIG. 16 shows atiming chart of a scanning signal 31, a data signal 32 and a voltage 33applied to the common electrode in the liquid crystal display apparatus.The definitions of the signals 31, 32 a, 32 b and 33 and the definitionof the arrow 34 are the same as the definitions of the signals 11, 12 a,12 b and 13 and the definition of the arrow 14 of FIG. 12, respectively.The scanning signal 31 is the same as the scanning signal 11 of FIG. 12.The alternating component of the data signal 32 changes in a cycleshorter than the horizontal period WH. The voltage 33 applied to thecommon electrode is always held at the center of amplitude of thealternating component of the data signal 32. Therefore, the liquidcrystal display apparatus is driven so that the voltage of the commonelectrode is always the same and that the voltages of all the pixelelectrodes are symmetrical with respect to the voltage of the commonelectrode.

FIG. 17A shows the polarities of the currents in all the pixels whichcurrents are for writing the voltages to be held into all the pixels inthe liquid crystal panel in a given frame in a case where the liquidcrystal display apparatus is driven by the use of the dot reversaldriving method. FIG. 17B shows the polarities of the currents in all thepixels in a frame next to the frame of FIG. 17A in the above-mentionedcase. The definitions of the rectangles, “+” and “−” of FIGS. 17A and17B are the same as the definitions of the rectangles, “+” and “−” ofFIGS. 13A and 13B.

The polarities of the currents flowing through the pixels of the liquidcrystal panel differ between the first frame and the next frame. In bothof the first and the next frames, the polarities of the currents flowingthrough two adjoining pixels in one column are different from each otherand the polarities of the currents flowing through two adjoining pixelsin one row are different from each other. Consequently, when thevoltages are written into all the pixels in the row on one of thescanning lines, the directions of flow of the currents for writing thevoltages into two adjoining pixels are opposite to each other, so thatthe currents flowing from the two adjoining pixels cancel each otherout. Therefore, the voltage of the common electrode is stabilized, sothat the voltage held by the pixel electrode does not vary.

Conventional liquid crystal display apparatuses of which liquid crystalpanel is driven by the use of the dot reversal driving method include anactive-matrix liquid crystal display apparatus of Japanese Publicationfor Laid-Open Patent Application Hei 5-341732 (1993). In this liquidcrystal display apparatus, in accordance with the amplitude of thealternating component of the data signal, the voltage of the commonelectrode is regulated so as to be always the same as the center ofvoltage variation of the pixel electrode.

In a liquid crystal display apparatus using the dot reversal drivingmethod, for example, the active-matrix liquid crystal display apparatusof JP-A 5-341732, the integrated circuit constituting the source driverrequires a driving voltage approximately twice the driving voltagerequired by the integrated circuit constituting the source driver in theliquid crystal display apparatus using the line reversal driving method.Therefore, while a so-called low withstand process can be used for thelatter integrated circuit, it is necessary to use an intermediatewithstand process for the former integrated circuit. Therefore, the sizeof the integrated circuit of the liquid crystal display apparatus usingthe dot reversal driving method is larger than the size of theintegrated circuit of the liquid crystal display apparatus using theline reversal driving method, and the number of masks necessary formanufacturing the former integrated circuit is greater than the numberof masks necessary for manufacturing the latter integrated circuit.Consequently, the manufacturing process of the integrated circuit of theliquid crystal display apparatus using the dot reversal driving methodis more complicated than the manufacturing process of the integratedcircuit of the liquid crystal display apparatus using the line reversaldriving method.

From these, the manufacturing cost of the integrated circuit of theliquid crystal display apparatus using the dot reversal driving methodis higher than the manufacturing cost of the integrated circuit of theliquid crystal display apparatus using the line reversal driving method.Moreover, since the integrated circuit of the liquid crystal displayapparatus using the dot reversal driving method employs the intermediatewithstand process, it is necessary that the power circuit for supplyingpower for driving the integrated circuit withstand higher voltages thanconventional power circuits. For this reason, it is necessary to newlydevelop a power circuit that withstands voltages of at least 10 V.

As described above, when the liquid crystal display apparatus of theabove-described structure is driven by the use of the line reversaldriving method, the display quality of the liquid crystal displayapparatus is reduced due to shadowing and nonuniformity in brightness.When the liquid crystal display apparatus of the above-describedstructure is driven by the use of the dot reversal driving method, it isimpossible to use the low withstand process for the driver in the liquidcrystal driving portion, so that the manufacturing cost of the liquidcrystal display apparatus increases.

SUMMARY OF THE INVENTION

An object of the invention is to provide a liquid crystal displayapparatus and a method of driving a liquid crystal panel capable ofpreventing the display quality from being reduced and capable ofreducing the manufacturing cost of the liquid crystal driving portion.

The invention provides a method of driving a liquid crystal panel whichincludes of a plurality of pixels arranged in a matrix form, theplurality of pixels each being composed of a pair of electrodes andliquid crystal sandwiched therebetween, and being divided into aplurality of pixel groups each composed of plural pixels,

the method comprising:

performing a predetermined computing operation at intervals of apredetermined horizontal period by the use of gradation datarepresentative of gradations of pixels of one of the pixel groups;

correcting a voltage decided on the basis of gradation data of eachpixel of the one pixel group, on the basis of a result of the computingoperation, to obtain a corrected voltage thereof; and

applying the corrected voltage between a pair of electrodes of eachpixel of the one of the pixel groups during the horizontal period.

According to the invention, the liquid crystal panel is driven by theabove-described driving method. Consequently, the voltage between thepair of electrodes for each pixel of the one pixel group is corrected onthe basis of the computation result. Consequently, even when a voltagebetween the pair of electrodes of each pixel of the one pixel groupvaries due to the gradation data for the one pixel group, the voltagebetween the pair of electrodes of each pixel can be made a voltage whichis in accordance with the gradation represented by the gradation datafor the one pixel group. As a result, when the display panel is drivenby the driving method, the display quality of the liquid crystal panelis enhanced as compared with that by the conventional driving method.

The invention is characterized in that the computing operation is anoperation of adding the gradation data.

According to the invention, in the method of driving a liquid crystalpanel, the gradation data is added to one another. Consequently, thecorrection voltages are obtained based on the gradation data and the sumof the gradation data. That is, the voltage between the pair ofelectrodes in each pixel of the one of the pixel groups is correctedbased on the sum of the plurality of gradation data. As a result, thecomputing operation of the gradation data is facilitated.

The invention provides a liquid crystal display apparatus comprising:

a liquid crystal panel constituted of a plurality of pixels arranged ina matrix form, the plurality of pixels each including a pair ofelectrodes and liquid crystal sandwiched therebetween, and being dividedinto a plurality of pixel groups each composed of plural pixels,

computing means for performing a predetermined computing operation atintervals of a predetermined horizontal period by the use of gradationdata representative of gradations of pixels of one of the pixel groups;

correction voltage setting means for correcting a voltage decided on thebasis of gradation data of each pixel of the one pixel group, on thebasis of a result of the computing operation, to obtain a correctedvoltage thereof; and

voltage applying means for applying the corrected voltage between a pairof electrodes of each pixel of the one of the pixel groups during thehorizontal period.

According to the invention, the liquid crystal display apparatusincludes the above-described constitution. Therefore, the voltagebetween the pair of electrodes in each pixel of one of the pixel groupsis corrected based on the result of the computing operation everyhorizontal period. Consequently, the voltage between the pair ofelectrodes in each pixel can be made a voltage that is in accordancewith the gradations represented by the gradation data even when thevoltage of one of the pair of electrodes in each pixel varies due to thegradation data. As a result, the liquid crystal display apparatus isbetter than the conventional liquid crystal display apparatus in displayquality.

The invention is characterized in that the computing operation is anoperation of adding the gradation data.

According to the invention, the computing means of the liquid crystaldisplay apparatus obtains the sum of the gradation data. Consequently,the corrected voltage is obtained based on each gradation data and thesum of the gradation data. As a result, the structure of the computingmeans is simplified and the computing operation is facilitated.

The invention is characterized in that the liquid crystal displayapparatus further comprises correction signal generating means forgenerating a correction signal associated with correction of the voltageon the basis of the result of the computing operation and supplying thecorrection signal to the correction voltage setting means in synchronismwith the horizontal period,

and the correction voltage setting means obtains the correction voltageon the basis of the gradation data and the correction signal every timethe correction signal is supplied.

According to the invention, the liquid crystal display apparatuscomprises the correction signal generating means for outputting thecorrection signal representative of the result of the computingoperation in synchronism with the horizontal period which is interposedbetween the computing means and the correction voltage setting means.Consequently, the correction voltage setting means can obtain thecorrection voltage at intervals of the horizontal period in response tothe correction signal instead of in response to the result of thecomputing operation by the computing means. That is, the correctionvoltage setting means can obtain the correction voltage in synchronismwith the horizontal period.

The invention is characterized in that the computing means outputs a bitstring representative of the result of the computing operation and thatthe correction signal generating means generates the correction signalon the basis of a part of bits of the bit string.

According to the invention, the correction signal generating means ofthe liquid crystal display apparatus generates the correction signal bythe use of only a part of the bits of the bit string representative ofthe result of the computing operation. Consequently, the number of bitsof a bit string representative of the correction signal is smaller thanthe number of bits of the bit string representative of the result of thecomputing operation. As a result, the number of input terminals of thecorrection voltage setting means of a case where the correction signalis supplied can be made smaller than the number of input terminals ofthe correction voltage setting means of a case where the result of thecomputing operation is directly supplied, and the circuit scale of theliquid crystal display apparatus of the case where the correction signalis supplied can be made smaller than the circuit scale of the liquidcrystal display apparatus of the case where the result of the computingoperation is directly supplied. When the correction signal is generatedby the use of only a part of the bits, the closer the number of bits ofthe part is to the number of all the bits of the bit stringrepresentative of the result of the computing operation, the higher theaccuracy of the correction voltage is.

The invention is characterized in that the computing means outputs a bitstring representative of the result of the computing operation and thatthe correction signal generating means generates the correction signalon the basis of all the bits of the bit string.

According to the invention, the correction signal generating means ofthe liquid crystal display apparatus generates the correction signal bythe use of all the bits of the bit string representative of the resultof the computing operation. In this case, the correction signalgenerating means may output the bit string as the correction signal asit is or may generate a correction signal including bits fewer in numberthan the bits of the bit string by performing computing operations onall the bits. Consequently, the correction voltage set by the correctionvoltage setting means is highest in accuracy. As a result, ahighest-display-quality liquid crystal display apparatus can beattained.

The invention is characterized in that the liquid crystal displayapparatus further comprises a reference power source for generating apredetermined reference voltage, and that the correction voltage settingmeans comprises:

reference voltage correcting means for correcting the reference voltageon the basis of the result of the computing operation;

voltage dividing means for dividing the corrected reference voltage toobtain a plurality of divisional voltages in accordance with all thegradations that the pixels can take; and

selecting means for selecting from among the plurality of divisionalvoltages a plurality of divisional voltages in accordance with thegradation represented by each gradation data as the correction voltages.

According to the invention, the correction voltage setting means of theliquid crystal display apparatus has the above-described structure.Consequently, since the reference voltage is corrected based on theresult of the computing operation, the plurality of divisional voltagescorrespond to the voltages obtained by correcting based on the result ofthe computing operation the voltages corresponding to all the gradationsthat the pixels can take. As a result, the correction voltage settingmeans can easily set the correction voltage.

The invention is characterized in that the reference voltage correctingmeans and the voltage dividing means are formed in a single integratedcircuit.

According to the invention, the reference voltage correcting means andthe voltage dividing means are formed on a single integrated circuit.This is for the following reasons: Generally, when a multiplicity ofintegrated circuits are manufactured, there are variations incharacteristics of parts in the integrated circuits, for example,resistance values of the resistors due to the manufacturing process ofthe integrated circuits. Therefore, when the reference voltagecorrecting means and the voltage dividing means are formed in twodifferent integrated circuits, the variations in characteristics ofparts differ between the reference voltage correcting means and thevoltage dividing means. However, when the reference voltage correctingmeans and the voltage dividing means are formed in a single integratedcircuit, the variations in characteristics of parts are the same betweenthe reference voltage correcting means and the voltage dividing means.Therefore, the variations in characteristics in the entire correctionvoltage setting means are smaller when the reference voltage correctingmeans and the voltage dividing means are formed in a single integratedcircuit than when the reference voltage correcting means and the voltagedividing means are formed in two different integrated circuits. That is,the variations in characteristics of parts due to the manufacturingprocessing of the integrated circuits can be restrained in the entirecorrection voltage setting means. Moreover, since the number ofintegrated circuits in the liquid crystal display apparatus is smallerwhen the reference voltage correcting means and the voltage dividingmeans are formed in one integrated circuit than when the referencevoltage correcting means and the voltage dividing means are formed intwo different integrated circuits, the cost of the parts is reduced andthe assembly of the liquid crystal display apparatus is facilitated.From these, it is preferable that the reference voltage correcting meansand the voltage dividing means be formed in a single integrated circuit.

The invention provides a liquid crystal display apparatus comprising:

a liquid crystal panel constituted of a plurality of pixels arranged ina matrix form, the plurality of pixels each being composed of a pair ofelectrodes and liquid crystal sandwiched therebetween, and being dividedinto a plurality of pixel groups each composed of plural pixels,

first voltage holding means for causing one of the pair of theelectrodes of each of all the pixels to hold a first voltage that ischanged at intervals of a predetermined horizontal period;

computing means for performing a predetermined computing operation atintervals of a predetermined horizontal period by the use of gradationdata representative of gradations of pixels of one of the pixel groups;

second voltage setting means for obtaining at intervals of thehorizontal period a second voltage by correcting on the basis of aresult of the computing operation by the computing means a voltagedecided on the basis of the gradation data and the first voltage; and

second voltage holding means for causing the other one of the pair ofelectrodes of each of all the pixels in one of the pixel groups to holdthe second voltage during the horizontal period.

According to the invention, the first voltage holding means of theliquid crystal display apparatus supplies the voltage that is changed atintervals of the horizontal period, to one of the electrodes in eachpixel. That is, the liquid crystal display apparatus uses the so-calledline reversal driving method. Therefore, the structure for driving theliquid crystal panel in the liquid crystal display apparatus, namely thefirst voltage holding means and the second voltage holding means can berealized by so-called low withstand process. Moreover, since the secondvoltage is supplied to the other one of the electrodes in each pixel,the voltage between the pair of electrodes in each pixel is a voltageobtained by correcting based on the result of the computing operation avoltage decided based on the gradation data. Therefore, for example, thequality degradation of the image displayed on the liquid crystal paneldue to shadowing or nonuniformity in brightness is prevented. As aresult, the liquid crystal display apparatus of the invention is betterthan the conventional liquid crystal display apparatus using the linereversal driving method in display quality.

From these, in the liquid crystal display apparatus of the invention, abetter-display-quality liquid crystal panel can be made than that in theconventional liquid crystal display apparatus using the line reversaldriving method, and the cost of the structure for driving the liquidcrystal panel can be made lower than that of the structure of theconventional liquid crystal display apparatus using the dot reversaldriving method. Moreover, in the liquid crystal display apparatus of theinvention, the display quality is prevented from being reduced when thesize of the liquid crystal panel is increased and when the number ofpixels in the liquid crystal panel is increased.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

Other and further objects, features, and advantages of the inventionwill be more explicit from the following detailed description taken withreference to the drawings wherein:

FIG. 1 is a block diagram showing the electric structure of a liquidcrystal display apparatus 41 according to an embodiment of theinvention;

FIG. 2 is a view showing an equivalent circuit of a liquid crystal panel43 provided in the liquid crystal display apparatus 41;

FIG. 3 is a schematic view showing the structure of one given pixel 58in the liquid crystal panel 43 and the structure of a peripheral part ofthe pixel 58 in the liquid crystal panel 43;

FIG. 4 is a block diagram showing the electric structure of acorrection-controlling circuit 62 provided in the liquid crystal displayapparatus 41;

FIG. 5 is a block diagram showing the electric structure of a sourcedriver 46 provided in the liquid crystal display apparatus 41;

FIG. 6 is a block diagram showing the electric structure of alevel-correcting circuit 77 and a gradation-voltage-generating circuit78 provided in the source driver 46;

FIG. 7 is a block diagram showing the electric structure of a bitcomputing circuit 100 provided in the liquid crystal display apparatus41;

FIG. 8 is a block diagram showing the electric structure of acorrection-controlling circuit 106 provided in the liquid crystaldisplay apparatus 41;

FIG. 9 is a block diagram showing the electric structure of alevel-correcting circuit 107 and the gradation-voltage-generatingcircuit 78 provided in the source driver 46;

FIG. 10 is a block diagram showing the electric structure of the sourcedriver 1 provided in the conventional liquid crystal display apparatus;

FIG. 11 shows a timing chart of a plurality of scanning signals suppliedto a plurality of scanning lines in the liquid crystal panel provided inthe liquid crystal display apparatus 1;

FIG. 12 shows a timing chart of one of the scanning signals, one of aplurality of scanning signals supplied to a plurality of gate lines inthe liquid crystal panel, and the voltage applied to the commonelectrode in the liquid crystal panel when the liquid crystal displayapparatus 1 is driven by the use of the line reversal driving method;

FIGS. 13A and 13B are views showing the polarities of the currentsflowing through all the pixels in the liquid crystal panel in a givenframe and a frame next to the frame when the liquid crystal displayapparatus 1 is driven by the use of the line reversal driving method;

FIG. 14 is a view showing the equivalent circuit of the liquid crystaldisplay apparatus 1;

FIG. 15 is a view showing the difference of the voltage to be held bythe pixel electrode caused due to the data signal when the liquidcrystal display apparatus 1 is driven by the use of the line reversaldriving method;

FIG. 16 shows a timing chart of one of the scanning signals, one of aplurality of scanning signals supplied to a plurality of gate lines inthe liquid crystal panel, and the voltage applied to the commonelectrode in the liquid crystal panel when the liquid crystal displayapparatus 1 is driven by the use of the dot reversal driving method; and

FIGS. 17A and 17B are views showing the polarities of the currentsflowing into all the pixels in the liquid crystal panel in a given frameand a frame next to the frame when the liquid crystal display apparatus1 is driven by the use of the dot reversal driving method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now referring to the drawings, preferred embodiments of the inventionare described below.

FIG. 1 is a block diagram showing the electric structure of a liquidcrystal display apparatus 41 according to an embodiment of theinvention. FIG. 2 is a view showing an equivalent circuit of a liquidcrystal panel 43 in the liquid crystal display apparatus 41. FIG. 3 is aschematic view showing the structure of a single pixel in the liquidcrystal panel 43 and the structure of a peripheral part of the pixel inthe liquid crystal panel 43. FIGS. 1 to 3 will be described together.The liquid crystal display apparatus 41 is connected, for example, to acomputer main unit 40 so as to be used as a display apparatus for thecomputer main unit 40.

The liquid crystal display apparatus 41 includes the liquid crystalpanel 43 and a driving portion 42. The driving portion 42 includes acontrol circuit 44, a level correction computing circuit 45, a sourcedriver 46, a gate driver 47 and a reference power source 49. In thisembodiment, it is assumed that the liquid crystal panel 43 is aso-called XGA panel capable of color display. While the source driver 46is divided into two integrated circuits in this embodiment, the sourcedriver 46 may be a single integrated circuit or may be divided intothree or more integrated circuits.

The liquid crystal panel 43 has a structure such that a liquid crystallayer is sandwiched between a pair of substrate members. One of the pairof substrate members includes one main substrate, a plurality ofscanning lines 51, a plurality of data lines 52, a plurality ofthin-film transistors (hereinafter, referred to as “TFTs”) 53, aplurality of pixel electrodes 54, and a plurality of auxiliary capacityportions 55. The other one of the pair of substrate members includes onetransparent counter substrate, one common electrode 56 and color filters57.

The plurality of scanning lines 51, the plurality of data lines 52, theplurality of TFTs 53, the plurality of pixel electrodes 54 and theplurality of auxiliary capacity portions 55 are arranged on one surfaceof the main substrate in the manner described below. The plurality ofscanning lines 51 are arranged parallel to one another. The plurality ofdata lines 52 are arranged parallel to one another and vertically to thescanning lines 51. The plurality of TFTs 53 are disposed one in thevicinity of each of a plurality of intersections P of the scanning lines51 and the data lines 52. The plurality of pixel electrodes 54 arearranged parallel to the scanning lines 51 and the data lines 52, sothat the pixel electrodes 54 are arranged in a matrix. The gate terminaland the source terminal of each of the TFTs 53 are connected to a singlescanning line 51 and a single data line 52 situated closest to the TFT53, respectively. The pixel electrodes 54 are connected to the drainterminals of the TFTs 53. The auxiliary capacity portions 55 arecapacitors, and are interposed between the pixel electrodes 54 and thescanning lines 51 other than the scanning lines 51 to which the pixelelectrodes 54 are connected through the TFTs 53. The common electrode 56is disposed on one surface of the counter substrate. The color filtersare disposed on one surface of the counter substrate. The one surface ofthe main substrate and the one surface of the counter substrate areopposed to each other with a liquid crystal layer LC therebetween.

The portions of the liquid crystal panel 43 where the pixel electrodes54 are opposed to the common electrode 56 with the liquid crystal layertherebetween act as the pixels 58. That is, the common electrode 56 iscommon to all the pixels 58. The portions of the common electrode 56that are opposed to the pixel electrodes 54 will be referred to ascounter portions 59. The color filters 57 are disposed so that one colorfilter 57 is superposed on each pixel when the liquid crystal panel 43is viewed from a direction parallel to the normal of the one surface ofthe counter substrate. In the equivalent circuit of FIG. 2, the commonelectrode 56 is shown as all the counter portions 59 connected byconductors 60 each having a resistance component rc.

The pixels 58 are all arranged in a matrix in the liquid crystal panel43. A set of a plurality of pixels 58 linearly arranged in a directionparallel to the scanning lines 51 will be referred to as a “row”,whereas a set of a plurality of pixels 58 linearly arranged in adirection parallel to the data lines 52 will be referred to as a“column”. In FIG. 3, the main substrate and the counter substrate arenot shown. In this embodiment, since the liquid crystal panel 43 is anXGA panel capable of color display, the pixels 58 are arranged in amatrix with 768 rows and 1028×RGB columns, and the color filters 57 areformed so as to include a plurality of red, blue and green filters.Given three pixels on which single red, blue and green filters aresuperposed correspond to one given pixel of a plurality of pixelsconstituting a color image to be displayed on the liquid crystal panel43, and the brightness, the hue and the chroma of the one pixel can beexpressed by adjusting the gradations of the three image elements.

The gradation of one of the pixels 58 is decided in accordance with thevoltage between the pair of electrodes in the pixel 58, that is, thedifference ΔV between the voltage held by the counter portion 59 and thevoltage held by the pixel electrode 54. In this embodiment, it isassumed that the higher the gradation of one of the pixels 58 is, thehigher the voltage ΔV between the pair of electrodes 54 and 59 in thepixel 58 is. That is, it is assumed that the higher the gradation of oneof the pixels 58 is, the farther the voltage held by one data line 52connected to the pixel electrode 54 in the pixel 58 through the TFT 53is away from the voltage held by the common electrode 56.

The control circuit 44 converts the image data supplied from thecomputer main unit 40 into a video signal of a configuration that can behandled in the liquid crystal display apparatus 41. In this embodiment,it is assumed that the video signal is a so-called 6 bits×RGB videosignal. That is, the video signal includes image element data forexpressing the brightness, chroma and hue of each of a plurality ofimage elements constituting the color image represented by the imagedata. It is assumed that each image element data includes threegradation components for deciding the gradations of the three pixels,that is, the R component, the G component and the B component. Thegradation of each of the pixels 58 is selected from among predeterminedplural levels of gradations that the pixels 58 can take. In thisembodiment, it is assumed that each of the gradation components is 6-bitdata and represents one of 64 levels of gradations. The video signal issupplied from the control circuit 44 to the level correction computingcircuit 45 and to the source driver 46.

The reference power source 49 outputs predetermined first and secondreference voltages Vref0 and Vref63. One of the first and the secondreference voltages Vref0 and Vref63 may be of ground level. The levelcorrection computing circuit 45, briefly, generates a correction signalassociated with gradation voltage correction in accordance with thevideo signal. To do this, the level correction computing circuit 45includes an adding circuit 61 and a correction-controlling circuit 62.

Every time a single horizontal period 1H elapses, the adding circuit 61captures a data input portion used for deciding the gradations of allthe pixels within the horizontal period (in the row on one of thescanning lines). The portion includes gradation components the number ofwhich is the same as the number of all the pixels in one of the rows.Hereinafter, the portion will be referred to as “unit portion”. Theadding circuit 61 adds all the gradation components in the captured unitportion at intervals of the horizontal period 1H. That is, the addingcircuit 61 obtains the sum of the numerical values corresponding to thegradations shown by all the gradation components in the unit portion.The adding circuit 61 supplies the correction-controlling circuit 62with at least a part of a bit string representative of the sum. In thisembodiment, the part is the highest eight digits of the bit stringrepresentative of the sum. The correction-controlling circuit 62generates the correction signal based on the part of the bit stringrepresentative of the sum, and supplies the correction signal to thesource driver 46.

In the description that follows, it is assumed that when all the bits inthe bit string representative of one given gradation component are “1”,the gradation shown by the gradation component is the maximum gradationof the 64 levels of gradations that the pixels can take and that whenall the bits in the bit string representative of one given gradationcomponent are “0”, the gradation shown by the gradation component is theminimum gradation of the 64 levels of gradations that the pixels cantake. Moreover, it is assumed that the numerical value corresponding tothe maximum gradation is “63” in decimal notation and that the numericalvalue corresponding to the minimum gradation is “0” in decimal notation.For example, when all the bits in the bit string representative of theunit portion are 1, all of the gradations shown by the gradationcomponents in the unit portion are the maximum gradation. In this case,as shown by expression (1), the sum of all the gradation components inthe unit portion is “193536” in decimal notation and “11111010000000000”in binary notation.

6 bits×RGB×1024 pixels=63×3×1024=193536  (1)

The source driver 46 receives the correction signal at intervals of thehorizontal period 1H and corrects an output voltage. The data signalsbecome correction voltages corresponding to the gradations shown by thegradation components in the unit portion.

In response to a horizontal synchronizing signal, the gate driver 47generates scanning signals the number of which is the same as the numberof scanning lines 51, and supplies the scanning signals to all thescanning lines 51 of the liquid crystal panel 43. At intervals of thepredetermined display period, the scanning signals are held at a levelfor turning on the TFTs 53, for example, high level during thehorizontal period 1H, and are held at a level for turning off the TFT53, for example, low level during the period other than the horizontalperiod 1H. The frame display period is, for example, an integralmultiple of the horizontal period 1H. Consequently, there is continuitybetween one of the data lines 52 and the pixel electrode 54 connected tothe data line 52 through the TFT 53 only when the TFT 53 is ON. Thecommon electrode is AC-driven at intervals of the horizontal period 1H.The scanning signals and the voltage signals applied to the commonelectrode 63 are the same as the scanning signals and the voltagesignals applied to the common electrode described in the prior art withreference to FIGS. 11 and 12. Consequently, there is continuity betweenone of the data lines 52 and the pixel electrode 54 connected to thedata line 52 through the TFT 53 only when the TFT 53 is ON, and avoltage in accordance with the gradation of the pixel including thepixel electrode 54 is written into the pixel while the TFT 53 is ON. Thepolarities of the currents flowing through the pixels to write thevoltage are as described with reference to FIGS. 13A and 13B.

Consequently, the liquid crystal panel 43 is driven by the use of theso-called line reversal driving method, and voltages in accordance withthe gradations of the pixels are written into all the pixels in theliquid crystal panel 43, so that the image represented by the image datasupplied from the computer main unit 40 is displayed on the liquidcrystal panel 43 as one frame. Thus, the driving portion 42 drives theliquid crystal panel 43 by the use of the so-called line reversaldriving method. Therefore, the source and the gate drivers 46 and 47 canbe realized by the so-called low withstand process. As a result, theproduct cost of the liquid crystal display apparatus 41 is lower thanthe product cost of the conventional liquid crystal display apparatususing the so-called dot reversal driving method.

FIG. 4 is a block diagram showing the electric stricture of thecorrection-controlling circuit 62. The correction-controlling circuit 62includes D flip-flops 63(1) to 63(N) the number of which is the same asthe number N of bits constituting the part of the bit stringrepresentative of the sum of all the gradation components in the unitportion. In this embodiment, it is assumed that the number N of bits iseight. A given integer not less than 1 and not more than N isrepresented as “n”.

A plurality of bits D(0) to D(N−1) constituting the part of the bitstring representative of the sum are supplied to the data inputterminals D of the plurality of D flip-flops 63(1) to 63(N),respectively. A latch strobe signal LS from the control circuit 44 issupplied to the clock input terminals CK of all the D flip-flops 63(1)to 63(N). Consequently, the D flip-flops 63(n) latch the bits D(n−1) inresponse to the latch strobe signal LS, and when the latched bits D(n−1)are “1”, the voltages at the output terminals Q of the D flip-flops63(n) are set at one voltage of predetermined two voltages and when thelatched bits D(n−1) are “0”, the voltages at the output terminals Q areset at the other voltage of the two voltages. In this embodiment, it isassumed that the one voltage is of high level and the other voltage isof low level.

Consequently, in response to the latch strobe signal LS, the levels ofthe output terminals Q of the D flip-flops 63(1) to 63(N), that is, thelevels of components α(1) to α(N) constituting the correction signal aredecided based on the bits D(0) to D(N−1). The components α(1) to a (N)are supplied from the correction-controlling circuit 62 to the sourcedriver 46 in parallel. The correction signal is a set of the componentsα(1) to α(N). The components α(1) to α(N) are binary signals. The numberof components α(1) to α(N) is the same as the number of D flip-flops63(1) to 63(N), that is, the number N of bits,

FIG. 5 is a block diagram showing the electric structure of the sourcedriver 46. The source driver 46 includes a video signal input portion67, a voltage setting portion 68 and an output circuit 69. The videosignal input portion 67 includes an input latch circuit 72, a shiftregister 73, a sampling memory 74 and a hold memory 75. The voltagesetting portion 68 includes a level-correcting circuit 77, agradation-voltage-generating circuit 78 and a D/A converter 76. Theinput latch circuit 72, the shift register 73, the sampling memory 74,the hold memory 75, the D/A converter 76 and the output circuit 29 arethe same as the input latch circuit 2, the shift register 3, thesampling memory 4, the hold memory 5, the D/A converter 6 and the outputcircuit 8 in the source driver 1 of the conventional liquid crystaldisplay apparatus.

The image data in the video signal is supplied to the input latchcircuit 72 so that the three pixel components are parallel to oneanother, and is latched. To the shift register 73, the clock signal CKand an input synchronizing signal SPI for controlling the operation ofthe video signal input portion 67 are supplied from the control circuit44. The latch strobe signal LS is supplied to the hold memory 75. Thecorrection signal is supplied to the level-correcting circuit 77. Thefirst reference voltage Vref0 is supplied to the level-correctingcircuit 77, whereas the second reference voltage Vref63 is supplied tothe gradation-voltage-generating circuit 78. The number of cells in theshift register 73 is, for example, a third of the number of columns ofthe pixels in the liquid crystal panel 43.

The video signal input portion 67 captures the unit portion from thevideo signal in response to the latch strobe signal LS. The timing wherethe video signal input portion 67 captures the unit portion of the videosignal is the same as the timing where the adding circuit 61 adds allthe gradation components in the unit portion. Therefore, the addingcircuit 61 and the video signal input portion 67 capture the sameportion of the video signal within the single horizontal period 1H.

Specifically, first, the shift register 73 captures the start pulse SPIin synchronism with the clock signal CK, and the captured start pulseSPI is the sampling timing of the sampling memory 74. Based on thesampling timing supplied from the shift register 73, the sampling memory74 samples the video signal latched by the input latch circuit 72.Consequently, the unit portion of the video signal is stored in thesampling memory 74. Then, the unit portion of the video signal istransferred from the sampling memory 74 to the hold memory 75 at a timein synchronism with the latch strobe signal LS. The hold memory 75latches the transferred unit portion in the video signal and transfersthe unit portion to the D/A converter 76.

Then, based on the gradation components in the unit portion of the videosignal captured by the video signal input portion 67, the voltagesetting portion 68 decides the voltages to be held by the data lines 52in order to decide the gradations of the pixels in one columncorresponding to the unit portion in the liquid crystal panel 43. Theone column corresponding to the unit portion is, of the all the pixelcolumns in the liquid crystal panel 43, one column where the gradationsof the pixels are decided based on the gradation components in the unitportion.

Specifically, first, the level-correcting circuit 77 corrects thereference voltage Vref0 based on the correction signal. Then, based onthe corrected gradation voltage Vref0′, the gradation-voltage-generatingcircuit 78 generates gradation voltages V0′ to V63 the number of whichis the same as the number of a plurality of gradations that the pixels58 can take. The plurality of gradation voltages are associated with oneof the plurality of gradations that the pixels can take. In thisembodiment, it is assumed that 64 levels of gradation voltages V0′ toV63 are generated and that the higher the gradation voltages V0′ to V63are, the closer the associated gradations are to the maximum gradationthat the pixels can take. Then, based on the gradation components in theunit portion of the video signal transferred from the hold memory 75,the D/A converter 76 selects, as the voltage to be applied to each ofthe data lines 52, one gradation voltage corresponding to each of thegradations shown by the gradation components from among the 64 levels ofgradation voltages V0′ to V63. The selected plurality of gradationvoltages are transferred from the D/A converter 76 to the output circuit69.

Thus, the level-correcting circuit 77 corrects the reference voltageVref0 in accordance with the correction signal, that is, in accordancewith the sum of all the gradation voltages in the unit portion.Consequently, the plurality of gradation voltages V0′ to V63 correspondto the voltages obtained by correcting in accordance with the correctionsignal a plurality of voltages corresponding to all the gradations thatthe pixels can take in the conventional liquid crystal displayapparatus. That is, the plurality of gradation voltages V0′ to V63correspond to the voltages obtained by correcting in accordance with thecorrection signal the 64 levels of voltages obtained by dividing therange from the reference voltage Vref0 to the reference voltage Vref63into 64 levels. Therefore, the voltages selected by the D/A converter76, that is, the voltages to be applied to the data lines 52 correspondto the voltages obtained by correcting in accordance with the sum thevoltages corresponding to the gradations shown by the gradationcomponents in the conventional liquid crystal display apparatus.

Therefore, only by adding the level-correcting circuit 77 to theconventional voltage setting portion, that is, the voltage generatingcircuit 78 and the D/A converter 76, the voltage setting portion 68 cancorrect the voltages corresponding to the gradations shown by thegradation components in the conventional liquid crystal displayapparatus in accordance with the sum. Consequently, the voltage settingportion 68 can easily set the voltages to be applied in accordance withthe sum.

The output circuit 69 impedance-converts the plurality of gradationvoltages selected by the D/A converter, that is, the plurality ofvoltages to be applied to the data lines 52, thereby generating aplurality of data signals. The data signals are supplied from the outputcircuit 69 to the data lines 52 of the liquid crystal panel 43 duringthe horizontal period 1H.

FIG. 6 is a block diagram showing the concrete electric structure of thelevel-correcting circuit 77 and the gradation-voltage-generating circuit78.

The level-correcting circuit 77 includes correction resistors 81(1) to81(N) the number of which is the same as the number N of the componentsα(1) to α(N) of the correction signal, and analog switches ASW(1) toASW(N) the number of which is the same as the number of correctionresistors 81(1) to 81(N). The correction resistors 81(1) to 81(N) areconnected in series in this order. The first correction resistor 81(1)has one terminal thereof connected as an input terminal 82 of thelevel-correcting circuit 77 to the first output terminal of a pluralityof terminals of the reference power source 49 for outputting the firstreference voltage Vref0, and has the other terminal thereof connected tothe second correction resistor 81(2). The last correction resistor 81(N)has one terminal thereof connected to the correction resistor 81(N−1)immediately preceding the last resistor, and has the other terminalthereof connected to a terminal of the gradation-voltage-generatingcircuit 78 as an output terminal 83 of the level-correcting circuit 77.The analog switches ASW(1) to ASW(N) are connected to the correctionresistors 81(1) to 81(N) in parallel. That is, the two terminals of theanalog switches ASW(1) to ASW(N) are connected across the correctionresistors 81(1) to 81(N).

The analog switches ASW(1) to ASW(N) are opened and closed in responseto the levels of the first to the N-th components α(1) to (N) of thecorrection signal. When the level of a component α(n) is the level of acase in which the bit D(n) of the correction signal is “1”, an analogswitch ASW(n) corresponding to the component α(n) is closed, and whenthe level is the level of a case in which the bit D(n) is “0”, theanalog switch ASW(n) is opened. That is, when the level of the componentα(n) is the level of the case in which the bit D(n) is “1”, theterminals of a correction resistor 81(n) connected to the analog switchASW(n) in parallel are short-circuited.

The resistance value of one given correction resistor 81(n) is higherthan the sum of the resistance values of all the resistors 81(n+1) to81(N) that succeed the correction resistor 81(n). Therefore, when thenumber N of bits is 8, the resistance values aR, bR, cR, dR, eR, fR, gRand hR of the correction resistors 81(1) to 81(8) satisfy therelationships of expressions (2) to (8) shown below. “R” is apredetermined resistance value. Coefficients “a” to “h” are decidedbased on at least one of the resistance value and the capacity value ofthe data line 52.

gR>hR  (2)

fR>gR+hR  (3)

eR>fR+gR+hR  (4)

dR>eR+fR+gR+hR  (5)

cR>dR+eR+fR+gR+hR  (6)

bR>cR+dR+eR+fR+gR+hR  (7)

aR>bR+cR+dR+eR+fR+gR+hR  (8)

The overall resistance value of the level-correcting circuit 77 dependson the combination of opening and closing of the analog switches ASW(1)to ASW(N). The combination of opening and closing corresponds to thecombination of the levels of the components α(1) to α(N), that is, thepart of the bit string representative of the sum of all the gradationcomponents in the unit portion. When the resistance values of thecorrection resistors 81(1) to 81(N) satisfy the relationships of theexpressions, the higher the digit, in the part of the bit string, of thebit for deciding the level of the component α(n) supplied to the analogswitch ASW(n) connected to the correction resistor 81(n) in parallel is,the higher the resistance value of the resistor 81(n) is. Therefore, thehigher the numerical value represented by the part of the bit string is,the higher the overall resistance value of the level-correcting circuit77 is. Consequently, the higher the numerical value represented by thepart of the bit string is, that is, the larger the sum is, the smallerthe drop amount of the first reference voltage Vref0 is.

The gradation-voltage-generating circuit 78 includes, for example,voltage dividing resistors 86(1) to 86(K) the number of which is smallerby one than the number of the gradation voltages. The voltage dividingresistors 86(1) to 86(K) are all connected in series in this order. Thefirst voltage driving resistor 86(1) has one terminal thereof connectedto the output terminal 83 of the level-correcting circuit 77 as a firstinput terminal of the gradation-voltage-generating circuit 78, and hasthe other terminal thereof connected to the second voltage dividingresistor 86(2). The last voltage dividing resistor 86(K) has oneterminal thereof connected to the voltage dividing resistor 86 (K−1)immediately preceding the last resistor, and has the other terminalthereof connected to a second output terminal of a plurality ofterminals of the reference power source 49 for outputting the secondreference voltage Vref63. To a connection point 87(0) between the oneterminal of the first voltage dividing resistor 86(1) and the outputterminal 83 of the level-correcting circuit 77, to connection points87(1) to 87 (K−1) between the voltage dividing resistors 86(1) to 86(K)and to a connection point 87(K) between the last voltage dividingresistor 86(K) and the second output terminal of the reference powersource 49, voltage obtaining conductors 89(0) to 89(K) for obtaining thevoltages at the contact points 87(0) to 87(K) as the gradation voltagesV0′ and V63 are connected.

Therefore, the gradation-voltage-generating circuit 78 divides thedifference between the second reference voltage Vref63 and the voltagelevel of the output terminal 83 of the level-correcting circuit 77, thatis, the corrected first reference voltage Vref0′ into the number thesame as the number of gradations that the pixels can take. In thisembodiment, the first gradation voltage V0′ of the 64 levels ofgradation voltages V0′ to V63 equals the corrected first referencevoltage Vref0′, whereas the last gradation voltage V63 of the 64 levelsof gradation voltages V0′ to V63 equals the second reference voltageVref63.

The gradation-voltage-generating circuit 78 is not limited to theabove-described structure but may have a different structure as long asthe range from the corrected first reference voltage Vref0′ to thesecond reference voltage Vref63 can be divided into the number the sameas the number of gradations that the pixels can take. For example, astructure may be used in which first resistors the number of which issmaller than the number of gradation voltages are interposed between theoutput terminal 83 of the level-correcting circuit 77 and the secondoutput terminal of the reference power source 49, a plurality of secondresistors connected in series are connected across the resistors inparallel, and the voltage difference ΔVref divided into a plurality ofnumbers by the first resistors is further divided by the secondresistors.

Thus, the basic structure of the level-correcting circuit 77 comprisesresistors and analog switches, and the basic structure of thegradation-voltage-generating circuit 78 comprises resistors.Consequently, the basic structures of the level-correcting circuit 77and the gradation-voltage-generating circuit 78 are extremely simple. Asa result, the circuit scale of the voltage setting portion 68 isprevented from increasing, and increase in the manufacturing cost of theliquid crystal display apparatus 41 is curbed.

It is preferable that at least the level-correcting circuit 77 and thegradation-voltage-generating circuit 78 be formed within a singleintegrated circuit. This is because variations in characteristics of theparts in the voltage setting portion 68 due to the manufacturing processof the integrated circuit are curbed more when the level-correctingcircuit 77 and the gradation-voltage-generating circuit 78 are formed inone integrated circuit than when the level-correcting circuit 77 and thegradation-voltage-generating circuit 78 are formed in two differentintegrated circuits. The characteristics of the parts are, for example,the resistance values of the resistors. Moreover, since the number ofintegrated circuits in the liquid crystal display apparatus 41 issmaller when the circuits 77 and 78 are formed in one integrated circuitthan when the circuits 77 and 78 are formed in two integrated circuits,the part cost of the liquid crystal display apparatus 41 is reduced andthe assembly of the liquid crystal display apparatus 41 is facilitated.In the liquid crystal display apparatus 41 of this embodiment, thelevel-correcting circuit 77 and the gradation-voltage-generating circuit78 together with the other parts 72 to 76 and 68 of the source driverconstitute one integrated circuit.

Of the liquid crystal panel driving methods of the driving portion 42,the behavior for causing the data lines 52 to hold voltages inaccordance with the gradations of the pixels will hereinafter bedescribed with reference to FIGS. 1 to 6. In parallel with the behavior,the gate driver 47 controls the TFTs 53 through the gate lines and thecommon electrode 63 is AC-driven. The behaviors of the gate driver 47and the common electrode 63 are the same as the behaviors of the gatedriver and the common electrode of the conventional liquid crystaldisplay apparatus.

For example, as a first example, a case is assumed in which the part ofthe video signal sampled by the sampling memory 76, that is, all thegradation components in the unit portion of the video signal representthe maximum gradation that the pixels can take. In this case, thevoltages between the pairs of electrodes 54 and 59 in all the pixels inthe column corresponding to the unit portion in the liquid crystal panel43 are the highest of the voltages that can be held between the pair ofelectrodes 54 and 59. In this case, the result of addition by the addingcircuit 61, that is, the bit string representative of the sum of all thegradation components is “11111010000000000”.

In response to the latch strobe signal LS, the correction-controllingcircuit 62 captures the highest order eight bits of the addition result,that is, “11111010” and decides the levels of the components α(1) toα(N) of the correction signal. In the first example, the first to thefifth and the seventh components α1 to α5 and α7 are of high level,whereas the sixth and the eighth components α6 and α8 are of low level.Consequently, the first to the fifth and the seventh analog switchesASW1 to ASW5 and ASW7 are closed and the sixth and the eighth analogswitches ASW 6 and ASW8 are opened. Therefore, the equivalent circuit ofthe level-correcting circuit 77 is a circuit in which the sixth and theeighth correction resistors R6 and R8 are connected in series.

As a second example, a case is assumed in which all the gradationcomponents in the unit portion of the video signal show the minimumgradation that the pixels can take. In this case, the bit stringrepresentative of the sum of all the gradation components is“00000000000000000”. In response to the latch strobe signal LS, thecorrection-controlling circuit 62 captures the highest order eight bitsof the addition result, that is, “00000000” and decides the levels ofthe components α(1) to α(N) of the correction signal. In the secondembodiment, since the captured bits are all 0, the levels of thecomponents α1 to α8 are all low. Consequently, the analog switches ASW1to ASW8 are all opened. Therefore, the equivalent circuit of thelevel-correcting circuit 77 is a circuit in which the correctionresistors R1 to R8 are all connected in series.

Comparing the first example and the second example, the sum of theresistance values of the resistors interposed between the first outputterminal of the reference power source 49 and thegradation-voltage-generating circuit 78, that is, the overall resistancevalue of the level-correcting circuit 77 in the second example is higherthan the overall resistance value of the level-correcting circuit 77 inthe first example. Therefore, the drop amount of the first referencevoltage Vrefφ in the second example is larger than the drop amount ofthe first reference voltage Vrefφ in the first example. From the above,the greater the number of maximum gradations included in the gradationsshown by all the gradation components in the unit portion is, the morethe level-correcting circuit 77 decreases the drop amount of the firstreference voltage Vref0. That is, the closer the voltages between thepair of electrodes in the pixels in the column corresponding to the unitportion in the liquid crystal panel 43 are to the maximum voltage thatcan be held between the pair of electrodes 54 and 59, the smaller thecorrected reference voltage difference is. This is for the followingreason:

In the liquid crystal panel 43 driven by the line reversal drivingmethod, the voltage held by the common electrode 56 drops due to thevoltages of all the data signals supplied to the liquid crystal panel 43during one horizontal period. Therefore, due to the voltage drop, thevoltage actually held by the common electrode 56 is closer to thevoltages of the data signals than to the ideal voltage to be held by thecommon electrode 56. The smaller the voltages of all the data signalsare, the larger the difference between the voltage actually held by thecommon electrode 56 and the ideal voltage is. The closer the voltagebetween the pair of electrodes 54 and 59 in the pixel 58 to which thevoltage corresponding to the gradation is written by a single datasignal is to the maximum voltage of the plurality of levels of voltagesthat can be held between the pair of electrodes 54 and 59, the lower thevoltage of the data signal is. In this embodiment, the closer thegradation of the pixel is to the maximum gradation, the closer thevoltage held between the pair of electrodes 54 and 59 of the pixel 58 isto the maximum voltage. Therefore, the greater the number of maximumgradations included in the gradations shown by all the gradationcomponents in the unit portion is, the larger the difference is.

Consequently, the greater the number of data signals, among all the datasignals, the voltages of which are the maximum voltage is, the more thedrop amount of the first reference voltage Vref0 is reduced, and thegreater the number of data signals, among all the data signals, thevoltages of which are the minimum voltage is, the drop amount of thefirst reference voltage Vref0 is increased. That is, in this embodiment,the greater the number of maximum gradations included in the gradationsshown by all the gradation components in the unit portion is, the morethe drop amount of the first reference voltage Vref0 is curbed.Consequently, the greater the number of data signals, among all the datasignals, the voltages of which are the maximum voltage is, the lower thecorrected first reference voltage Vref0′ is. When the gradation voltagesV0′ to V63 are generated by the use of the first reference voltageVref0′ thus corrected, the gradation voltages V0′ to V63 are the same asthe voltages obtained by correcting in accordance with the magnitude ofthe difference the voltage obtained by dividing the range between thetwo reference voltages Vref0 and Vref63 into 64 levels. That is, thevoltages of the data signals are corrected in accordance with themagnitude of the difference.

Consequently, the nonuniformity in brightness among a plurality ofcolumns in the image displayed on the liquid crystal panel 43 iseliminated and the quality of the image displayed on the liquid crystalpanel 43 is prevented from being degraded due to the generation ofso-called shadowing. From these, in the liquid crystal display apparatus41 of this embodiment, the liquid crystal panel 43 can be made better indisplay quality than the conventional liquid crystal display apparatususing the line reversal driving method, and the driving portion 42 canbe made in lower cost than the structure for driving the liquid crystalpanel of the conventional liquid crystal display apparatus using the dotreversal driving method. In addition, in the liquid crystal displayapparatus 41 of this embodiment, the display quality reduction due toincrease in the size of the liquid crystal panel 43 can be prevented andthe display quality reduction due to increase in the number of pixels inthe liquid crystal panel 43 can be prevented.

The first reference voltage Vref0 may be corrected based on a numericalvalue other than the sum of the gradations shown by all the gradationcomponents in the unit portion of the video signal as long as it is anumerical value representing how close the voltages between the pair ofelectrodes 54 and 59 in the pixels 58 in the column corresponding to theunit portion of the video signal are to the maximum voltage that can beheld between the pair of electrodes 54 and 59. For example, thenumerical value other than the sum maybe the result of a division inwhich the sum of the gradations is divided by a predetermined constant,or may be the average of the gradations shown by all the gradationcomponents in the unit portion. When the sum is used for the correctionof the first reference voltage Vref0, the computing portion forobtaining the numerical value, that is, the adding circuit 61 can berealized by a typical adding circuit. Therefore, it is preferable to usethe sum for the correction of the first reference voltage Vref0 becausethe structure of the computing portion is simplified and the computingoperation for obtaining the numerical value is facilitated.

The correction-controlling circuit 62 of the liquid crystal displayapparatus 41 of this embodiment generates the correction signal by theuse of only the highest eight digits of the bit string representative ofthe result of the computing operation by the adding circuit 61. The partof the bit string used for the generation of the correction signal isnot limited to the highest eight digits but may be a different part. Thenumber of bits of the part is not limited to eight but may be adifferent number. Which part of the bit string is used for thegeneration of the correction signal is decided, for example, accordingto display characteristics of the liquid crystal panel 63. For example,of the bit string, the eight odd-numbered bits counted from the firstbit may be set as the part. Moreover, for example, of the bit string,the eight even-numbered bits counted from the first bit may be set asthe part.

Thus, when only a part of the bit string is used for the generation ofthe correction signal, the number of components of the correction signalis smaller than the number of bits of the bit string. Therefore, thenumber of input terminals of the source driver 46 for inputting thecorrection signal can be made smaller than the number of input terminalsfor inputting the bit string when the bit string is directly supplied tothe source driver 46, and the circuit scale of the driving portion 42when the correction signal is supplied to the source driver 46 can bemade smaller than the circuit scale of the driving portion when the bitstring is directly supplied to the source driver 46. When the firstreference voltage Vref0 is corrected by the use of only a part of thebit string, the closer the number of bits of the part is to the numberof all the bits of the bit string, the higher the correction accuracy ofthe corrected first reference voltage Vref0′ is.

Further, the correction-controlling circuit 62 may produce a bit stringincluding fewer bits than the bit string representative of the sum byperforming a predetermined computing operation on all the bits of thebit string representative of the sum obtained by the adding circuit 61and generate the correction signal by the use of the produced bitstring. To do so, for example, a bit computing circuit 100 shown in FIG.7 is interposed between the adding circuit 61 and thecorrection-controlling circuit 62. The bit computing circuit 100includes OR circuits 101(1) to 101(J) the number J of which is smallerthan the number of bits of the bit string representative of the sum. TheOR circuits 101(1) to 101(J) are all arranged in parallel. In FIG. 7, itis assumed that the number J of OR circuits is eight.

To the OR circuits 101(1) to 101(J), a plurality of continuous bits inthe bit string representative of the sum are inputted to obtain thelogical product of the plurality of bits. For example, in the example ofFIG. 7, to the first OR circuit 101(1), the seventeenth and thesixteenth bits a17 and 16 counted from the first bit of the bit stringrepresentative of the sum are inputted. To the second OR circuit 101(2),the fifteenth and the fourteenth bits a15 and 14 counted from the firstbit of the bit string representative of the sum are inputted. To theseventh OR circuit 101(7), the fifth and the fourth bits a5 and a4counted from the first bits of the bit string representative of the sumare inputted. To the eighth OR circuit 101(8), the third to the firstbits a3 to a1 counted from the first bit of the bit stringrepresentative of the sum are inputted.

Consequently, a number, J, of logical products are obtained. In theexample of FIG. 7, the following logical products are obtained: thelogical product of the seventeenth and the sixteenth bits a17 and a16;the logical product of the fifteenth and the fourteenth bits a15 and 14;. . . ; the logical product of the fifth and the fourth bits a5 and a4;and the logical product of the third to the first bits a3 to a1. Insteadof the bits of the part of the bit string representative of the sum, thenumber, J, of the logical products are inputted to the data inputterminals D of the D flip-flops 63(1) to (N) of thecorrection-controlling circuit 62. In this case, the number, J, of thelogical products and the number, N, of the D flip-flop are the same.

In the liquid crystal display apparatus 41 of this embodiment, thecorrection signal is supplied to the source driver 46 n as it is. Inthis case, since the eight components of the correction signal issupplied to the source driver 46 in parallel, the source driver of thisembodiment has eight more input terminals than the source driver of theconventional liquid crystal display apparatus. In order to reduce thenumber of input terminals for inputting the correction signal, aso-called 8 to 3 decode circuit and a so-called 3 to 8 decode circuitmay be interposed between the correction-controlling circuit 61 and thesource driver 46 and between the input terminal and the level-correctingcircuit 77 in the source driver 46, respectively.

Consequently, first, the correction signal is supplied to the sourcedriver 46 after the eight components are converted into three sets ofelectric signals by the 8 to 3 decode circuit. Then, the three sets ofelectric signals are supplied to the level-correcting circuit 77 afterde coded into the eight components by the 3 to 8 decode circuit.Therefore, the number of input terminals of the source driver 46 forinputting the correction signal can be reduced from eight to three. Thetwo circuits for performing the conversion and the decoding are notlimited to the 8 to 3 decode circuit and the 3 to 8 decode circuit butmay be different circuits as long as the circuits are a convertingcircuit for converting the eight components into less than eightelectric signals and a reconstituting circuit capable of reconstitutingthe eight components from the electric signals without any error.

The correction-controlling circuit 62 may generate the correction signalby the use of all the bits of the bit string representative of the sumobtained by the adding circuit 61. To do so, the correction-controllingcircuit 62 and the level-correcting circuit 77 are replaced by acorrection-controlling circuit 106 of FIG. 8 and a level-correctingcircuit 107 of FIG. 9. The correction-controlling circuit 106 of FIG. 8is the same as the correction-controlling circuit 62 of FIG. 4 exceptthat the number N of D flip-flops 63(1) to 63(N) is the same as thenumber M of all the bits of the bit string and that the bits to beprocessed are changed from the bits constituting a part of the bitstring to all the bits of the bit string. In this embodiment, it isassumed that the number M of all the bits is 17. Therefore, thecorrection signal comprises the components α(1) to α(M) the number ofwhich is the same as the number M of all the bits, and the componentsα(1) to α(M) are supplied to the source driver 46 in parallel. Thelevel-correcting circuit 107 of FIG. 9 is the same as thelevel-correcting circuit 77 of FIG. 6 except that the number of thecorrection resistors 81(1) to 81(N) and the number of analog switchesASW(1) to ASW(N) are the same as the number of components α(1) to α(M)of the correction signal, that is, the number M of all the bits.

Like the level-correcting circuit 77 of FIG. 6, the resistance value ofone correction resistor 18(m) of the seventeen correction resistors81(1) to 81(M) in the level-correcting circuit 107 is higher than thesum of the resistance values of all the resistors 81(m+1) to 81(M) thatsucceed the one resistor 81(i). “m” is an integer not less than 1 andnot more than M. That is, the resistance values aR, bR, cR, dR, eR, fR,gR, hR, iR, jR, kR, lR, mR, nR, oR, pR and qR of the correctionresistors 81(1) to 81(17) satisfy the relationships of the followingexpressions (9) to (15):

pR>qR  (9)

oR>pR+qR  (10)

nR>oR+pR+qR  (11)

mR>nR+oR+pR+qR  (12)

lR>mR+nR+oR+pR+qR  (13)

kR>lR+mR+nR+oR+pR+qR  (14)

·

aR>bR+cR+dR+eR+fR+gR+hR+iR+jR+kR+lR+mR+nR+oR+pR+qR . . .   (15)

Thus, the liquid crystal display apparatus to which the bit stringcomputing circuit 100 of FIG. 7 is added and the liquid crystal displayapparatus using the correction-controlling circuit and thelevel-correcting circuit of FIGS. 8 and 9 are capable of correcting thefirst reference voltage Vref0 for the correction of the gradationvoltages by the use of all the bits of the bit string representative ofthe sum. Consequently, the correction accuracy of the plurality ofgradation voltages is the highest. As a result, a best-display-qualityliquid crystal display apparatus can be attained.

The relationship between the voltages of the data signals and thegradations of the pixels 58 may be opposite to that of the descriptiongiven above. That is, the gradations of the pixels 58 into which thevoltages corresponding to the gradations are written by the data signalsmay be closer to the minimum gradation as the voltages of the datasignals become closer to the maximum voltage that the pixels 58 cantake. In this case, the greater the number of minimum gradationsincluded in the gradations shown by all the gradation components in theunit portion is, that is, the greater the number of data signals, amongthe plurality of data signals decided by the gradation components in theunit portion, the voltages of which are the maximum voltage is, the morethe drop amount of the first reference voltage Vref0 is necessarilyreduced. Therefore, by decreasing the overall resistance value of thelevel-correcting circuit 77 as the sum of the numerical valuescorresponding to the gradations shown by all the gradation components inthe unit portion decreases, the difference of the voltage of the commonelectrode 56 can be corrected. That is, the pixels voltages V0′ to V63are made closer to the first reference voltage Vref0 as the sum of thevoltages of all the data signals decided by the plurality of gradationcomponents in the unit portion increases. The liquid crystal displayapparatus 41 of this embodiment is an example of the liquid crystaldisplay apparatus of the invention and the method of driving a liquidcrystal panel of the invention and can be practiced in various otherforms as long as the principal operations are the same. Particularly,the detailed operations of the parts in the liquid crystal displayapparatus 41 are not limited to the ones shown above but may be realizedby different operations as long as the same processing results areobtained.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The presentembodiments are therefore to be considered in all respects asillustrative and not restrictive, the scope of the invention beingindicated by the appended claims rather than by the foregoingdescription and all changes which come within the meaning and the rangeof equivalency of the claims are therefore intended to be embracedtherein.

What is claimed is:
 1. A liquid crystal display apparatus comprising: aliquid crystal panel including a plurality of pixels arranged in amatrix form, the plurality of pixels each including a pair of electrodesand liquid crystal sandwiched therebetween, and being divided into aplurality of pixel groups each including a plurality of pixels;computing means for performing a predetermined computing operation atintervals of a predetermined horizontal period, using gradation datarepresentative of gradations of pixels of one of the pixel groups;correction voltage setting means for correcting a voltage determinedfrom gradation data of each pixel of the one pixel group, on the basisof a result of the computing operation to obtain a corrected voltage;voltage applying means for applying the corrected voltage between a pairof electrodes of each pixel of the one of the pixel groups during thepredetermined horizontal period; and correction signal generating meansfor generating a correction signal, associated with correction of thevoltage, on the basis of the result of the computing operation, and forsupplying the correction signal to the correction voltage setting meansin synchronism with the predetermined horizontal period; the correctionvoltage setting means obtains a correction voltage on the basis of thegradation data and the correction signal, each time the correctionsignal is supplied; wherein the computing means outputs a bit stringrepresentative of the result of the computing operation and wherein thecorrection signal generating means generates the correction signal onthe basis of at least some of the bits of the bit string.
 2. A liquidcrystal display apparatus comprising: a liquid crystal panel including aplurality of pixels arranged in a matrix form, the plurality of pixelseach including a pair of electrodes and liquid crystal sandwichedtherebetween, and being divided into a plurality of pixel groups eachincluding a plurality of pixels; computing means for performing apredetermined computing operation at intervals of a predeterminedhorizontal period, using gradation data representative of gradations ofpixels of one of the pixel groups; correction voltage setting means forcorrecting a voltage determined from gradation data of each pixel of theone pixel group, on the basis of a result of the computing operation toobtain a corrected voltage; voltage applying means for applying thecorrected voltage between a pair of electrodes of each pixel of the oneof the pixel groups during the predetermined horizontal period; andcorrection signal generating means for generating a correction signal,associated with correction of the voltage, on the basis of the result ofthe computing operation, and for supplying the correction signal to thecorrection voltage setting means in synchronism with the predeterminedhorizontal period; the correction voltage setting means obtains acorrection voltage on the basis of the gradation data and the correctionsignal, each time the correction signal is supplied; wherein thecomputing means outputs a bit string representative of the result of thecomputing operation wherein the correction signal generating meansgenerates the correction signal on the basis of all the bits of the bitstring.